In order to fully explain the level of the technology on the present invention at present, all explanations of patents, patent applications, Gazettes of patents and scientific papers cited or specified in the present application are incorporated into it by referring to them herein.
In the miniaturization of flash memory until the generation of 0.13 μm the main stream was to reduce the cell area using Floating Gate (FG) and to make the insulating film thinner. On the contrary, in the generation of 90 nm the trap type memory has been noticed, which makes use of the trap in the insulating film for the charge storage layer, because it has become difficult to make the insulating film thinner from a view point of securing the retention property.
As one of the trap type nonvolatile memory cells the patent literature 1 discloses a structure comprising first transistor sections including a charge storage layer for the information storage and second transistor sections for selecting a first transistor section. FIG. 1 shows a conventional structure disclosed in the patent literature 1 in which the structure comprises a MOS type of the first transistor section made of a insulating film 4 including a trap layer and a conductor 5 used for a memory conductive body, and another MOS type of the second transistor section consisting of a insulating film 7 and a conductor 8 used for a control conductive body, on a semiconductor substrate 1. In addition, the MOS is the collective term to a transistor of a field effect type with an insulating gate.
In addition, a structure with three layers consisting of a silicon oxide film, a silicon nitride film and a silicon oxide film is used for the insulating film 4 including the trap layer. Also, for the conductive body 5, silicon doped with n-type impurity is used. Also, for the insulating film 7 a silicon oxide film is used, and for the conductive body 8, silicon doped with n-type impurity is used.
The first transistor section and the second transistor section are separated by an insulating film 6 between electrodes. The first transistor section is used for the information storage, and the second transistor section is used for selecting the first transistor section. It is the feature in the conventional structure that the withstanding voltage of the second transistor section is lower than that of the first transistor section, namely the film thickness of the insulating film 4 including the trap layer is thinner than that of the insulating film 7. In the operation for reading data out, a stored data is read out on the bit line corresponding to whether or not electric current flows in accordance with the state of the threshold voltage in the first transistor section when the second transistor section with the nonvolatile memory cell is switched to ON state.
Since the second transistor section is thinner in the oxide film of the gate and smaller in the withstanding voltage than the first transistor section, it is possible to obtain relatively large trans-conductance (current drivability), using relatively lower gate voltage to the MOS transistor for selection, compared with the situation that both of the MOS transistor section for the memory retention and the MOS transistor for selection are formed with high withstanding voltages, thereby contributing to high speed in reading out. Herein, the lower the threshold voltage value in the first transistor section is set the more the electric current for reading out increases even at the lower voltage. However, it is necessary to be set at relatively higher level because the threshold voltage value in the second transistor section has a lower limit in view of suppression to the punch through electric current, namely the threshold voltage value in the second transistor section necessarily becomes more than the threshold voltage value in the first transistor section.
In the conventional structure setting of those threshold values have been implemented by adjusting impurity density in channel region 14 of the first transistor section and in channel region 15 of the second transistor section. Since the film thickness of the insulating film 7 is thinner than that of the insulating film 4 including the trap layer, the impurity density in the channel region 15 is necessary to be heightened, compared with the case that the film thickness of the insulating film 7 is thicker than that of the insulating film 4. There is a disadvantage that originally expected effect could not obtained, because the trans-conductance becomes lower even if the insulating film 7 is made thinner under the condition that the higher the impurity density becomes the more the impurity scattering of the carrier increases in the channel, and then the mobility becomes lower. Further, as the other problem in the conventional structure, there is a disadvantage that the electric current for reading out becomes lower by the occurrence of potential gaps between the channel regions because there is a gap between the first transistor section and the second transistor section.
In addition there is a disadvantage that it is impossible to implement common electrodes between the first transistor section and the second transistor section, because the second transistor section has a lower withstanding voltage and then the high voltage can not be applied thereto.    Patent literature 1: International publication WO2003/012878